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國立聯合大學 電子工程學系碩士班 陳勝利所指導 劉誌瑋的 高壓/超高壓N通道/P通道LDMOS電晶體之抗ESD能力提升研究 （2021），提出Emc local charge關鍵因素是什麼，來自於靜電放電、場板效應、保持電壓、橫向擴散金氧半電晶體、閂鎖效應、導通電阻、蕭特基二極體、矽控整流器、二次崩潰電流、傳輸線脈衝系統、元件觸發電壓。
而第二篇論文長庚大學 電子工程學系 王哲麒所指導 詹雅庭的 石墨烯電極於電阻式記憶體與仿生電子突觸之研究 （2020），提出因為有 石墨烯、氧化釓、氧化鋁、電阻式記憶體、電晶體、突觸的重點而找出了 Emc local charge的解答。
高壓/超高壓N通道/P通道LDMOS電晶體之抗ESD能力提升研究
為了解決Emc local charge 的問題，作者劉誌瑋 這樣論述：
製程技術的日新月異積體電路體積已進入奈米等級的時代，而靜電放電(Electrostatic Discharge；ESD)對於積體電路的可靠度是一個嚴重影響的問題。由於ESD的現象是靜電電荷轉移至低電位所造成的放電事件，且發生時間非常短暫快速且會產生高能量造成積體電路損壞。雖然製程技術一直在進步但面對外來的威脅卻沒有降低，且高壓與超高壓元件需要更大的佈局面積才能有同樣的防護能力，所以更需要效率更好的保護能力抵抗外部的威脅。因此本論文針對高壓及超高壓的LDMOS元件進行ESD防護能力提升及抗閂鎖效應能力強化設計之探討。由於LDMOS有較長的漂移區能使元件有更大的導通電阻(Ron)可以承受更高的電
壓，不過也導致超高壓與高壓LDMOS的高電場容易聚集在汲極端或淺溝槽隔離區(STI)。在高壓nLDMOS中也較容易有不均勻導通現象與保持電壓過低造成閂鎖效應發生，而pLDMOS的ESD防護能力與特性都比nLDMOS差且需要較大的佈局面積才能達到相同的防護能力。所以本論文中針對TSMC 0.5μm UHV BCD製程超高壓nLDMOS與0.18μm HV BCD製程n/pLDMOS進行強化佈局設計，利用在不同電極和漂移區之間添加不同層次或改變元件物理長度距離等方式，並透過傳輸線脈衝系統(TLP)、HBM機台等測試儀器獲得重要物理參數。論文中利用操作電壓及元件結構分成三大部分:首先在超高壓nLDM
OS利用寄生Schottky提升Vh，之後縮小漂移區長度調整工作電壓，使元件也能在低壓下工作，並且有更好的抗閂鎖能力。接著利用場板效應對Poly2施加不同電位，同時在漂移區離散P型層次及對閘極端做分離調變，改善漂移區峰值電場進而達到更好的ESD防護能力。第二部分在高壓65V nLDMOS汲極端利用寄生Schottky維持Vh並藉由寄生SCR路徑增加電流排放能力，使抗閂鎖效應能力與ESD防護能力可以達到相對平衡。在漂移區和源極端加入不同層次離散排列和增加漂移區長度藉此調整漂移區導通電阻，可以有效達到提升ESD防護能力。再來是將閘極端分離，藉由增加間距與分離閘的長度探討不同材料的場板距離與長度變化
對漂移區電場分布的改善。第三部分在高壓70V pLDMOS汲極端利用寄生Schottky和寄生SCR路徑，與原始pLDMOS相比在相同單位面積下防護能力有明顯提升，與nLDMOS防護能力之間的落差也縮小許多。而在漂移區增加長度及加入不同層次可以藉由調整導通電阻增加ESD防護能力。還有在源極端利用增加Well和不同排列方式來提升pLDMOS電流排放的截面積使ESD電流防護能力再增加。最後利用TCAD模擬驗證超高壓nLDMOS Poly2接不同電位調變之間的物理變化和與對比下線結果，顯示出其中的物理現象與量測結果相當吻合。藉由以上三大部分不同結構中的調變達到改善超高壓nLDMOS與高壓n/pLDM
OS元件的ESD可靠度，使元件ESD電流防護能力與抗閂鎖效應能力之間取得好的平衡。
石墨烯電極於電阻式記憶體與仿生電子突觸之研究
為了解決Emc local charge 的問題，作者詹雅庭 這樣論述：
Contents指導教授推薦書口試委員審定書謝誌 iii中文摘要 vAbstract viContents viiFigure Captions xTable Lists xviiiChapter 1 Introduction 11.1 Research Background 11.2 Next-generation Non-volatile Memory 21.2.1 Phase-change Random Access Memory (PRAM) 21.2.2 Magneto-resistive Random Access Me
mory (MRAM) 31.2.3 Ferro-electronic Random Access Memory (FRAM) 41.2.4 Resistive Random Access Memory (RRAM) 41.3 In-Depth Introduction to RRAM 51.3.1 Material of RS layer 51.3.2 Operation of RRAM 61.3.3 Mechanism of Resistive Switching 71.4 Graphene 91.5 Nervous System 10
1.6 Artificial Intelligence and Artificial Synapses 121.7 Motivation of This Study 141.8 Methodology 151.9 Organization of the Thesis 16Chapter 2 Interface Modification of Stacked Trilayer-Graphene/Metal Electrode on Resistive Switching of Silver Electrochemical Metallization Cells 24
2.1 Introduction 242.2 Experimental 262.2.1 Device Fabrication 262.2.2 Characterization 272.3 Results and Discussion 282.3.1 Material Analyses of Stacked TLG on Metal Films 282.3.2 Conductive Mechanisms 292.3.3 Energy Band Diagram and RS Mechanism 322.3.4 Reliability Behavior
s 342.4 Summary 35Chapter 3 Memristors with Hydrogen Plasma Surface Modified Compacted Self-Assembly Graphene Electrodes for Robust Artificial Electronic Synapses 573.1 Introduction 573.2 Experimental 593.2.1 Synthesis of CSA graphene 593.2.2 Device fabrication 603.2.3 Character
ization 613.3 Results and Discussion 623.3.1 Material Analyses of CSA Graphene 623.3.2 Memory Behaviors and RS Mechanisms 663.3.3 Characteristics of Artificial Synapses 713.4 Summary 73Chapter 4 Graphene Field-Effect Transistor with Different Gate Dielectrics for Artificial Synapse
Applications 924.1 Introduction 924.2 Experimental 944.3 Results and Discussion 954.3.1 Memory Behaviors and VDirac Switching Mechanisms 954.3.2 Characteristics of Artificial Synapses 984.4 Summary 101Chapter 5 Conclusion and Future Works 1215.1 Conclusion 1215.2 Future w
ork 122Reference List 123 Figure CaptionsFig. 1 1 (a) The cross-section schematic of the conventional PCM cell. (b) PCM cells are programmed and read by applying electrical pulses which change temperature accordingly. (c) I-V characteristics of set and reset state of phase change memory. 18
Fig. 1 2 Magnetoresistance of a MRAM as function of applied magnetic field. 18Fig. 1 3 The crystal structure of ferroelectric material and the P-E hysteresis loop of the FRAM. 19Fig. 1 4 The schematic of (a) 1T1R array architecture, (b) 1T1R element formed by integrating the RRAM stack on the
copper plug, (c) 3D 1D1R crossbar array structure, and (d) 1D1R storage element composed of a RRAM device and a diode connected in series. 19Fig. 1 5 Schematic diagram of the energy band of interface-dominated RS mechanism RRAM at HRS and LRS. 20Fig. 1 6 Schematic illustration of the resisti
ve switching process in VCM. 20Fig. 1 7 Schematic diagram of the operations of an electrochemical metallization memory cell. 21Fig. 1 8 The Schematic diagram of graphen, fullerenes, carbon nanotubes, and graphite. 21Fig. 1 9 The schematic illustration of the energy bands of the graphene.
22Fig. 1 10 The structure of a neuron. 22Fig. 1 11 Stages of an Action Potential. 23Fig. 1 12 The structure of a synapse. 23Fig. 2 1 The fabrication process of Ag-EMCs with TLG on different metal contacts. 36Fig. 2 2 Raman spectra of the graphene grown on a copper foil and transf
erred onto the Ni and Ir films. 36Fig. 2 3 (a) Bar chart of the surface roughness of the deposited Ir and Ni films and the SLG and TLG transferred onto the Ir and Ni films. (b) The AFM images of the TLG transferred onto the Ir and Ni flims. 37Fig. 2 4 Raman mapping of the (a) r-TLG and (b) B-T
LG for the Ag-EMC device fabrication. 38Fig. 2 5 Raman spectra of the r-TLG and B-TLG from Fig.2-4. 39Fig. 2 6 Cross-sectional HRTEM image and EDX mapping of the Ag/GdxOy/AlxOy/TLG/Ir structure. 39Fig. 2 7 The I−V characteristics of the forming process of the Ag-EMCs with different stacked
structures of the TLG on the contact metals. 40Fig. 2 8 Typical I−V characteristics of the Ag-EMCs with different stacked structures of the TLG on the contact metals. 40Fig. 2 9 Statistical distributions of (a) operation voltages, (b) resistances at the HRS and LRS, and the resistance ratio of
the Ag-EMCs with different stacked structures of the TLG on the contact metals. 41Fig. 2 10 J/T2 versus V0.5 fitting of the r-TLG/Ir sample at the positive TE bias of the (a) HRS and (b) LRS. 42Fig. 2 11 Temperature dependence of I−V curves of the r-TLG/Ir sample at the positive TE bias of th
e (a) HRS and (b) LRS. 43Fig. 2 12 J/T2 versus 1000/T fitting of the r-TLG/Ir sample at different TE biases of (a) HRS and (b) LRS. 44Fig. 2 13 The equivalent Schottky barrier height Ea versus V0.5 curve of the r-TLG/Ir sample at (a) HRS and (b) LRS. 45Fig. 2 14 (a) J versus V2 fitting of t
he B-TLG/Ir and TLG/Ni samples at the positive TE bias of the HRS. (b) Current versus voltage fitting of the B-TLG/Ir and TLG/Ni samples at the positive TE bias of the LRS. 46Fig. 2 15 (a) J versus V2 fitting of all samples at the negative TE bias of the HRS. (b) Current versus the absolute value
of the TE voltage fitting at logarithmic scales of all samples at the negative TE bias of the LRS. 47Fig. 2 16 Area dependence of the resistance at the HRS of all samples. 48Fig. 2 17 Area dependence of the resistance at the LRS of all samples. 49Fig. 2 18 Current versus voltage characteri
stics of the (a) r-TLG/Ir structure and (b) B-TLG/Ir and TLG/Ni structures. 50Fig. 2 19 The statistical distributions of the resistances at the HRS and LRS of all samples with different reset pulse operations. 51Fig. 2 20 The statistical distributions of the resistances at the HRS and LRS of a
ll samples with different set pulse operations. 52Fig. 2 21 Energy band diagrams of the (a) TLG/Ni sample, (b) B-TLG/Ir sample, and (c) r-TLG/Ir sample. 53Fig. 2 22 The RS mechanisms of the r-TLG/Ir sample at the (a) HRS and (b) LRS, the B-TLG/Ir sample at the (d) HRS and (e) LRS, and the TLG/
Ni sample at the (g) HRS and (h) LRS. The equivalent circuit diagrams of all samples at the LRS are shown in (c), (f) and (i). 53Fig. 2 23 The data retention characteristics of all samples at (a) 25 °C and (b) 55 °C. 54Fig. 2 24 The data retention characteristics of the TLG/Ni sample measured
at rising temperatures. 55Fig. 2 25 Endurance characteristics of the Ag-EMCs with different stacked structures of the TLG on the contact metals. 55Fig. 3 1 Fabrication procedures of the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs. 75Fig. 3 2 FE-SEM images of CSA
graphene films without and with H2 plasma surface modification for 1, 5, 10, and 15 min. 75Fig. 3 3 AFM images of CSA graphene films without and with H2 plasma surface modification for 1, 5, 10, and 15 min. 76Fig. 3 4 Raman spectra of CSA graphene films without and with H2 plasma surface modif
ication for 1, 5, 10, and 15 min. 77Fig. 3 5 FTIR of CSA graphene films without and with H2 plasma surface modification for 1, 5, 10, and 15 min. 77Fig. 3 6 (a) XPS O 1s spectra of CSA graphene films with different H2 plasma modification times; (b) a cumulative distribution of the PARs of each
peak from (a). 78Fig. 3 7 (a) XPS C 1s spectra of CSA graphene films with different H2 plasma modification times; (b) a cumulative distribution of the PARs of each peak from (a). 79Fig. 3 8 XPS N 1s spectra of CSA graphene films without and with H2 plasma surface modification for 1, 5, 10, an
d 15 min. 80Fig. 3 9 The statistical distributions of CPD of CSA graphene films with different H2 plasma modification times. 80Fig. 3 10 The statistical distributions of resistivity and mobility of CSA graphene films without and with H2 plasma surface modification for 1 to 15 min. 81Fig. 3
11 Forming characteristics of the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs. 81Fig. 3 12 The statistical distributions of the forming operating voltages for the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs. 82Fig. 3 13 Typical I–V charac
teristics of the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs. 82Fig. 3 14 The statistical distributions of (a) operating voltages and (b) resistances at HRS and LRS, and resistance ratio of the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs.
83Fig. 3 15 (a) Sinh−1 J versus voltage curves at positive TE bias of HRS and (b) ln(J) versus 1/E curves at positive TE bias of HRS for the GdxOy based memristors with H2 plasma surface modified CSA graphene BEs. 84Fig. 3 16 I-V fitting in double linear scale of the GdxOy memristors with H2 pla
sma surface modified CSA graphene BEs at negative TE bias of LRS. 85Fig. 3 17 Data retention of the GdxOy memristors with H2 plasma surface modified CSA graphene BEs. 86Fig. 3 18 Cycling endurance tests of the GdxOy memristors with H2 plasma surface modified CSA graphene BEs. 86Fig. 3 19 Il
lustrations of RS mechanisms of the GdxOy memristors with H2 plasma surface modified CSA graphene BEs at (a) initial state, (b) LRS, and (c) HRS. The schematic diagrams of chemical structures of CSA graphene flakes (d) without and with (e) appropriate and (f) excess H2 plasma surface modification.
87Fig. 3 20 Area dependence of the resistance at HRS and LRS of the GdxOy memristors with H2 plasma surface modified CSA graphene BEs. 88Fig. 3 21 (a) Potentiation and (b) depression behaviors of the GdxOy memristors without and with 10 min H2 plasma surface modified CSA graphene BEs. 89Fig.
3 22 STDP characteristics of the GdxOy memristors (a) without and (b) with 10 min H2 plasma surface modified CSA graphene BEs. 90Fig. 4 1 The structures of the transistors use top-gate or back-gate structure. 103Fig. 4 2 The transfer curve (Id–Vg) of GFET. [120] 103Fig. 4 3 The schematic d
iagram of the GFET structure. 104Fig. 4 4 Raman spectrum of the graphene channel before and after RIE etching. 104Fig. 4 5 The transfer Id-Vg characteristics with the hysteresis behavior of the (a) GdxOy- and (b) AlxOy-based-GFET. 105Fig. 4 6 The transfer Id-Vg characteristics of the (a) Gd
xOy- and (b) AlxOy-based-GFET after a +3 V, 1 s and −3 V, 1 s operation. 106Fig. 4 7 The cycling endurance tests of the (a) GdxOy- and (b) AlxOy-based-GFET. 107Fig. 4 8 The resistance of (a) Ir/GdxOy/graphene and (b) Ir/AlxOy/graphene structure during the cycling tests. 108Fig. 4 9 The C–V
curves of the (a) GdxOy- and (b) AlxOy-based-GFET after +3 V, 1 s/ −3 V, 1 s operation. 109Fig. 4 10 Flat band voltage versus oxide thickness of the (a) GdxOy- and (b) AlxOy-based-GFET. 110Fig. 4 11 The schematic diagrams of the bias applying at the (a) read and (b) operation process of the GF
ETs 111Fig. 4 12 The repeated potentiation and depression characteristics of the (a) GdxOy- and (b) AlxOy-based-GFET. 112Fig. 4 13 The design of the spikes for STDP measurement. 113Fig. 4 14 The STDP behaviors of the (a) GdxOy- and (b) AlxOy-based-GFET. 114Fig. 4 15 The LTP property of (
a) VDirac and (b) percentage versus time of the GdxOy-based-GFET after different operation cycles. 115Fig. 4 16 The LTD property of (a) VDirac and (b) percentage versus time of the AlxOy-based-GFET after different operation cycles. 116Fig. 4 17 The operation voltage for PPF measurement. 117
Fig. 4 18 The PPF behaviors of (a) ΔVDirac versus Δtpre and (b) PPF index versus Δtpre of the GdxOy-based-GFET. 118Fig. 4 19 The PPF behaviors of (a) ΔVDirac versus Δtpre and (b) PPF index versus Δtpre of the AlxOy-based-GFET. 119 Table ListsTable 2 1 Summary of the operation currents, voltage
s, and powers of the Ag-EMCs with different stacked structures of the TLG on the contact metals. 56Table 2 2 Summary of conductive mechanisms of of the Ag-EMCs with different stacked structures of the TLG on the contact metals at positive and negative TE biases of the HRS and LRS. 56Table 3 1
Summary of the performance between this chapter and some traditional artificial synapse devices. 91Table 4 1 Summary of the operation voltages of potentiation and depression and the representation of the postsynaptic potential between this chapter and some FET-based artificial synapse devices.
120